The external SPI master device starts by sending the Preamble bytes (0x70 and 0x50)
followed by a zero byte.
The DA1453x confirms the reception of the Preamble with 0x02 (Acknowledged) or 0x20 (Not Acknowledged) in case something went wrong.
Bytes 3 and 4 define the length of the payload to follow. The least significant byte is sent first. A length is a number that represents the amount of data in 32-bit words.
The SPI master must send the calculated checksum of the payload. The checksum is calculated by XORing every successive byte with the previous value. The initial checksum value is 0xFF.
Byte 6 defines the mode of operation directed by the SPI master (8, 16, or 32-bit modes) while the DA1453x SPI slave answers with ACK/NACK regarding the reception of the length bytes.
The mode is encoded as follows:
0x00 = 8-bit mode
0x01 = 16-bit mode
0x02 = 32-bit mode
0x03 = Reserved
Byte 8 is the last control byte. After the data bytes are sent, two additional dummies bytes 0x00 and 0x00 are sent by the master,
The DA1453x replies with 0xAA before the ACK (0x02) or NACK (0x20).
The data section is presented and takes into consideration the instructed mode. The stream of data is followed by two extra empty slots for the DA1453x to clock out the end of the FW download (0xAA) and the ACK/NACK (0x02/0x20).
Upon completion of the SPI master process, all related pads are set to input and pulled down.
For master clock frequencies over 1 MHz, a 1 us inter-byte space is needed
After resetting the slave 7 ms is needed to start SPI update for boot step 1 (toggle the P0_1 to high) and 8 ms until the slave response to the master, see Figure 7 and Figure 8
Master clock up to 16 MHz is supported when the DA1453x operates as a slave
Booting from an external SPI Slave is the fifth step in the booting sequence for the DA1453x and the sequence of events that takes place after the power-up is described in Table 2 followed by the power profile.
Table 2 is with respect to the BUCK mode wherein 13.1 kB (BLE Barebone) application is copied from the external Slave SPI with the speed of 2 MHz.
The onboard 2-Mbit SPI data flash memory is connected over SPI to the DA1453x and can be accessed over the SWD port. The description below will explain how to program the firmware into the Flash memory. The necessary motherboard jumper settings are shown in Figure 11 and Figure 12.
Figure 11 Jumper Settings on DA14531 DevkitP for SPI Flash (MX25R2035)
Figure 12 Jumper Settings on DA1453x DevkitP for SPI Flash (AT25DF021A)
In the SmartSnippets™ toolbox, from upper right side select board as shown in Figure 13 for the JTAG interface. Select the desired Target for your project:
Again on left upper bar select programmer and then select FlashCode tab click connect on bottom right tab and select Read as shown in Figure 15.
Figure 15 SPI Flash Programmer to Connect, Read and Burn the Hex File
At left bottom you can see Importfromfile , choose any hex/binari file you want to import and check the bootable option . Click next and then finnish.Now you can burn the file in your spi Flash memory.
Click Connect and if it prompts you to press the hardware Reset button, press the Reset button on the motherboard. Please look at the SmartSnippets™ Toolbox log to make sure the default jtag_programmer is loaded in the SysRAM.
Once connected, you can erase/read or Flash the program.
Click Burn to program the flash using the SPI slave interface. Check the SmartSnippets™ Toolbox log file to make sure the firmware is successfully programmed in the flash memory. Press the hardware RESET button on the motherboard and now the device will boot from the SPI flash.
In Development mode, the “Boot from Specific” flag will be evaluated. If the flag is programmed, new pin locations for booting from an external SPI slave to make DA1453x an SPI Master will be set. The “Boot from Specific” flag can be addressed when for instance booting FW from external SPI Flash with different SPI Pins assignment. The details of the configuration are presented below. If this path is entered, the system will always try to boot from UART so that the SPI Flash can be updated if needed. Any of the three UART configurations specified in Table 4 can be selected by writing bits [31:24] at the Boot specific config field in the OTP header. If booting from SPI Flash fails, the Booter will jump back to the normal scan sequence of the peripheral devices.
The advantages are that the booter will skip another scan sequence of peripheral devices, thereby reducing the boot time from SPI slave. From Figure 6, the boot step 1-4 time will thereby be negligible. Also, the SPI Clock speed can be increased to reduce the time to copy code from Flash to SysRAM.
Figure 25 is an example of the values set in the OTP header for the boot specific mode.
The table below is taken from the datasheet, section 4.4 OTP header.
Default (all other values) = Two-wire UART (P0_0/P0_1)
0x07F87FCC
Boot specific port
mapping
Boot specific port mapping:
- Bits[7:4] = SPI_CLK, Port number
- Bits[3:0] = SPI_CLK, Pin number
- Bits[15:12] = SPI_EN, Port number
- Bits[11:8] = SPI_EN, Pin number
- Bits[23:20] = SPI_DO, Port number
- Bits[19:16] = SPI_DO, Pin number
- Bits[31:28] = SPI_DI, Port number
- Bits[27:24] = SPI_DI, Pin number
In address 0x07F87FC8 which is boot specific config,
Bits[31:24]: 02 (1-wire UART P0_5)
Bits[23:16]: 7F (SPI_DIV, clock speed, 7F gives the maximum clock speed for SPI. 8MHz can be achieved using the DA14531 module)
Bits[15:8]: AB (wake up command opcode that flash memory responds to)
Bites[7:0] : AA (0xAA implies boot from SPI Port at a specific location)
In address 0x07F87FCC which is boot specific port mapping,
