5. Booting

The Booting is a vital process that starts up a Microcontroller Unit (MCU), getting both the software and hardware ready to work.

The boot process can be different for various MCUs, involving various firmware stages and hardware setups. Despite these differences, we can create a standard template to understand the boot process better.

Here are the four main steps in the boot sequence: Power-On Reset (Hardware Process): Initiates hardware operations during startup, ensuring a smooth and stable beginning.

Memory Aliasing (Remapping) and Architecture (Hardware Process): Modifies memory addresses and configures the hardware to enhance the MCU’s performance.

Firmware Booting (Hardware and Firmware Process): Initiates crucial software components using a combination of hardware and firmware.

Setting up external memory, loading, and executing: Before loading an image onto external memory (ensuring refresh rate, clock, etc.), setup procedures should be completed. Subsequently, the image can be loaded from flash to RAM.

BootRom

The term “BootRom” typically refers to a small piece of firmware or code stored in ROM that is responsible for initializing the hardware and starting the boot process.

5.1. BootROM Sequence

The DA1453x can boot from external serial devices when the OTP memory is not programmed. This is to enable the development of application code. At power-up, the system enters Development Mode, where the boot code decides which interface to boot from. This section describes the boot sequence for all supported serial interfaces and provides the developer with the necessary information to realize the protocol required to establish communication between an external device and the DA1453x. The DA1453x operates in two modes: Normal mode and Development mode. The decision on which mode the chip enters after power-up is taken by the boot code that resides in the ROM. A complete flow chart of the boot code is illustrated in Figure 5.

Figure 5 BootROM Sequence

When in Development mode, the boot ROM code initializes all serial peripheral devices from which the DA1453x might download the code. The options are:

• UART

• SPI (both master and slave)

• I2C (only master)

The boot ROM code searches for a valid response on various combinations of I/O’s one after the other. There is also the option that the user can define desired I/O’s with the use of a specific OTP field for the SPI interface. The boot pins and serial peripherals search sequence are presented in Booting options(Steps).

After the Configuration Script has been executed, the Booter has to decide whether the device is in Development or Normal mode by reading the two words indicated as application flags in the OTP. The OTP image is copied into RAM starting at address 0x0 by the Booter.

Configuration Script (CS)

The Configuration Script (CS) is a table of 32-bit entries and is 60 words deep, so in total the CS can utilize 240 bytes of space. The CS is used to program registers with values that are defined during production testing, to store a trim value for the application software, and to define the UART time-out timer during booting. It is executed by the Booter to prepare and initialize the system prior to that the CPU starts running the application code.

In Development mode, the “Boot from Specific” flag will be evaluated. If the flag is programmed, new pin locations for booting from an external SPI slave to make DA1453x an SPI Master will be set. The “Boot from Specific” flag addresses allowing for booting from a different pin configuration than the default one, so that the system can boot from an external FLASH using the development mode.If this path is entered, the system will always try to boot from UART so that the SPI Flash can be updated if needed. Any of the three UART configurations specified in Booting options(Steps) can be selected by writing bits [31:24] at the “Boot specific config” field in the OTP header. If booting from SPI Flash fails, the Booter will jump back to the normal scan sequence of the peripheral devices. If the Boot from Specific flag is not programmed, the system should continue with scanning the different serial interfaces to identify whether a device is connected to it. After OTP is disabled, six steps as described in Booting options(Steps) are performed. Before using the UART, the XTAL32M clock needs to be enabled. All the boot steps are protected by a timeout.

Figure 6 Booting options(Steps)

If no bootable devices are found on any of the serial interfaces, the Booter can do two things, depending on what is stored in the CS. If the “Debugger disable” (0x70000000) command is stored there, the Booter will start scanning for peripherals again. Otherwise, it enters the endless loop with the debugger (JTAG) being enabled. The debugger is connected to P0_10 in the FCGQFN24 package. After the BootROM sequence has completed, the default system clock is RC32M, regardless of which boot path has been chosen and all GPIOs are set back to their default reset values.

Boot sequence in DA1453x modules

In the DA1453x modules, pins (P0_0,P0_1,P0_3,P0_4) are already connected to the Onboard SPI flash as result , options 3(Boot from 1-wire UART(Second Option)), 4(Boot from2-wire UART) are not possible and we need to use option 2 by default.

In order to solve this limitation, The DA14535 module is pre-burnt by a secondary bootloader on on-board SPI flash. To have a better understanding about this please take a look to the DA14535 Module Getting Started with the DEVKITP and SmartBoot.

5.2. Timing Diagram of the Booting Sequence:

The boot ROM code execution time for booting from an external serial device is 17.3 ms. At the end of the scanning sequence, the device will halt with the JTAG enabled (if there is no disabling from the configuration script). Figure 7 displays the power-up sequence of the DA1453x and pins P0_0 to P0_5, which are involved in the 6 steps as explained in the booting sequence Booting options(Steps).

Figure 7 Scan Timing for Booting from External Serial Devices (DA14531)

figure below showing the actual time sequence overview of happening each step(option).

Figure 8 Step 1 to Step 6 of the Booting Sequences Zoomed in Picture (DA14531)

Figure 9 shows the scan timing from the external devices when there are no external devices available on any of the possible interfaces to boot from. The approximate time to boot from each peripheral is also noted.

Figure 9 Timing Diagram (DA14531)

As seen in the above Timing diagram, step 1 could not be captured in the zoomed-in figure. Please refer to Figure 8 for the capture. The booting of DA1453x is incredibly fast and the above timing diagram can help the developer to select the booting most suitable for their application.