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  • ble_app_all_in_one crashes with hardfault when program DA14535 Module
  • ble_app_lecb L2CAP application can’t handle different src and dest cids
  • ble_app_lecb L2CAP L2CAP app does not reject with Insuff. Auth. when necessary.
  • ble_app_lecb L2CAP app does not add credits to its own channel
  • The DA14585 and DA14531-00 do not include the complete ‘SMP Timeout after Security Request’ fix.
  • syscntl_dcdc_turn_on_in_boost_ROM() leads to a hardfault when DA14531-01 and DA14535 configured in bypass mode
  • Driver configuration structures are not compatible with ROM functions on LLVM
  • UART with DMA flow control
  • Improve error handling in case of AES issue
  • UART ROM driver: Not all baud rates are supported by the stack
  • Wrong register attributes allow modification of the device specific manufacturing data
  • Random number generator incorrectly seeded
  • DA14531 Temperature sensor driver in SDK
  • DA14531 prod_test otp_write function issue
  • DA14531 Trim value issue when waking up from hibernation with no ram retained
  • ADC interrupted with BLE activity
  • DA14585 Secondary Booter - Booting encrypted image bigger than 80KB
  • DA14531 IAR Example : Some missing configuration
  • SMP timeout caused by encryption request during SMP session
  • Always passing ATT_ERR_APP_ERROR in custs1_value_req_rsp_handler()
  • High temperature and RCX
  • PDM support
  • GLPS minor improvement
  • Weight Scale Service : Missing app-callback communication
  • DA14585/DA14586 Crystal trimming lost after sleep
  • Coexistence driver limits the pins for BLE_EIP from P00 up to P07
  • DA14531 ROM booter Limitations
  • I2C asynchronous slave reception
  • UART2 initialization infinite loop
  • Build error with PRODUCTION_DEBUG_OUTPUT enabled
  • HTPT Indication Problem
  • DA1453x bootROM boot specific configuration Limitation
  • Error in unused defines
  • Default system rand() function is not NIST compliant
  • HCI ACL fragmentation does not work correctly
  • Static Random BD Address calculation issue
  • Reset Indication characteristic not firing callback when status error is returned after first read
  • DA14531 Further secondary bootloader optimization for large image files
  • DA145x App_Easy_timer problem during long sleep time
  • Update XTAL32M settings to the robust settings as recommended in the HW guidelines
    • Description
    • Workaround
    • Reference
  • No GTL reply is sent to the host after a failed pairing attempt
  • SDK metric and RCX
  • DA14585 Peripheral does not generate GAPC_PARAM_UPDATED_IND
  • Secondary bootloader runs on both encrypted and un-encypted images
  • If during an SMP session the Master attempts to re-encrypt the link, the encryption request reaches the 531 Host after an SMP timeout is generated
  • ROM version of adc_input_shift_config() includes wrong delay
SDK6 Known Limitations List
  • Update XTAL32M settings to the robust settings as recommended in the HW guidelines

Update XTAL32M settings to the robust settings as recommended in the HW guidelines

ID: LPCBARESDK-859

Status: Fixed

First reported: 6.0.18.1182.1

Fixed in: 6.0.20.1338

Description

The default XTAL32M oscillator settings in the SDK6.0.18.1182.1 or earlier might lead in some cases to an interruption of oscillation

Workaround

Customers working with an earlier SDK version should change the current and amplitude settings of the XTAL32M. This fix will be included in the next release and we will introduce an improved current and amplitude setting for the XTAL32M oscillator.

XTAL32M_CTRL0_REG: CORE_CUR_SET = 1
XTAL32M_CTRL0_REG: CORE_AMPL_TRIM = 5

To achieve this, the SDK must be adapted in:

  • Location: sdk/platform/arch/main

  • Filename: arch_system.c

  • API name: system_init()

--- arch_system.c       2022-12-01 15:20:54.739927400 +0100
+++ arch_system.c       2022-11-23 18:05:32.000000000 +0100
@@ -1268,8 +1268,7 @@
     // Configure XTAL32M
     SetBits16(TRIM_CTRL_REG, XTAL_TRIM_SELECT, 2);       // only CLK_FREQ_TRIM_REG will be used for XTAL32M trimming
     SetBits16(XTAL32M_START_REG, XTAL32M_START, 0);
+    SetBits16(XTAL32M_CTRL0_REG, CORE_CUR_SET, 1);
+    SetBits16(XTAL32M_CTRL0_REG, CORE_AMPL_TRIM, 5);
-    SetBits16(XTAL32M_CTRL0_REG, CORE_CUR_SET, 2);
 #else
     // Confirm XTAL16M calibration
     xtal16m_calibration_check();

And

  • Location: sdk/platform/arch/main

  • Filename: arch_hibernation.c

  • API name: arch_hibernation_restore()

@@ -335,8 +335,7 @@
     // Configure XTAL32M
     SetBits16(TRIM_CTRL_REG, XTAL_TRIM_SELECT, 2);  // only CLK_FREQ_TRIM_REG will be used for XTAL32M trimming
     SetBits16(XTAL32M_START_REG, XTAL32M_START, 0);
+    SetBits16(XTAL32M_CTRL0_REG, CORE_CUR_SET, 1);
+    SetBits16(XTAL32M_CTRL0_REG, CORE_AMPL_TRIM, 5);
-    SetBits16(XTAL32M_CTRL0_REG, CORE_CUR_SET, 2);

     if ((clk_ctrl_reg_backup & RUNNING_AT_XTAL32M) == RUNNING_AT_XTAL32M)
     {

Additionally, make sure not to set the CLK_FREQ_TRIM_REG to 0x0 before going to sleep in:

  • Location: sdk/platform/arch/main

  • Filename: arch_main.c

  • API name: arch_switch_clock_goto_sleep()

delete

@@ -340,6 +340,9 @@
 #else
     while( (GetWord16(CLK_CTRL_REG) & RUNNING_AT_RC16M) == 0 );
 #endif
-    SetWord16(CLK_FREQ_TRIM_REG, 0);                        // Set zero value to CLK_FREQ_TRIM_REG
-    // Do not disable the XTAL16M (DA14585/586) or XTAL32M (DA14531).
-    // It will be disabled when we sleep...
 #endif // (USE_POWER_OPTIMIZATIONS)
     }
 }

Reference

Refer to the section 3.2.2.2 in AN-B-075 : DA14531/530 Hardware Guidelines

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