6.4. Flash Programmer
6.4.1. Overview
Flash programmer (flash_programmer) is a target side application used to upload and read back the application code that runs on platforms powered by the DA1453x/DA1458x series integrated circuit. After the flash programmer application is booted, the platform communicates over the UART or JTAG interface with the host application that allows it to read or write application code to the FLASH, EEPROM or OTP memory. Both sides exchange messages that contain operation codes, statuses and payload with respect to the defined protocol.
6.4.2. Enhanced Flash Programmer Security in SDK 6.0.24
The SECURE_AES_KEYS_IV_PROGRAMMER macro in da1455xx_config_basic.h has been introduced in SDK 6.0.24 to enhance cybersecurity.
This feature enables secure programming of AES keys and IVs, ensuring protection against unauthorized access.
/****************************************************************************************************************/
/* Enable the secure programming feature of the AES keys and IVs. */
/* Users should also define their secret unwrapping operation and key */
/****************************************************************************************************************/
#define SECURE_AES_KEYS_IV_PROGRAMMER (0)
Two new commands have been added to the flash programmer to handle AES keys securely:
#define ACTION_OTP_SECURE_READ_ENC_KEYS 0xD0
#define ACTION_OTP_SECURE_WRITE_ENC_KEYS 0xD1
The ACTION_OTP_SECURE_WRITE_ENC_KEYS (0xD1) command is used to store wrapped AES keys in one step. The flash programmer checks if the correct key size is written, then unwraps the keys and saves them in a secure storage area (OTP). If everything works, it returns a success message; if not, it gives an error.
The ACTION_OTP_SECURE_READ_ENC_KEYS (0xD0) command reads the stored keys, wraps them again, and sends them securely back to the PLT.
This following image Figure 89 illustrates the secure method for reading and writing application code to FLASH/EEPROM memory using the Flash Programmer and the newly introduced Cybersecurity Mechanism in SDK 6.0.24. The flash programmer communicates with an external host via UART and interacts with the DA1453x/DA1458x BLE device. A Secure Secondary Bootloader has been introduced Section 6.2, supporting encrypted and/or signed images, with up to five decryption and five verification keys.
Figure 89 Enhanced Flash Programming with Cybersecurity in SDK 6.0.24
6.4.3. Communication Channel
The communication channel is selected at compile time and is limited to the following options:
6.4.3.1. UART (USE_UART Flag Defined)
In this mode, flash programmer receives messages from the host and responds back with the UART interface. It also defines an exchange buffer of size 64K- 1 bytes (0xFFFF) for DA14585/585 targets and 32K - 1 bytes (0x7FFF) for DA1453x. This limits the amount of data that can be written or read in a single message. This is the implication of the 2 byte wide length indicator that (along with the checksum) is sent before the actual message frame. The frame length and the checksum code are not cached inside the buffer and holds only the actual message (including possible headers and payload).
With this knowledge it is easy to figure out, that in case of the OTP write operation, the actual firmware chunk size is limited to 0xFFF8 (0xFFFF minus the 7 bytes of header data for this particular message) for DA1458x and 0x7FF8 for DA1453x. As communication via UART is synchronous, the defined buffer is used for both the incoming and the outgoing messages.
The flash programmer communicates by default with the host through pins P0_0, P0_1 at speed 57600 for DA1458x targets and at speed 115200 for DA1453x. This can be changed by appending to the binary 1 byte. This byte selects pins and baud rate according to the following table.
Platform |
Selector |
TX pin |
RX pin |
Baud rate |
|---|---|---|---|---|
DA1458x |
0 (default) |
P0_0 |
P0_1 |
57600 |
2 |
P0_2 |
P0_3 |
115200 |
|
4 |
P0_4 |
P0_5 |
57600 |
|
6 |
P0_6 |
P0_7 |
9600 |
|
DA1453x |
0 (default) |
P0_0 |
P0_1 |
115200 |
3 (single wire UART) |
P0_3 |
P0_3 |
115200 |
|
5 (single wire UART) |
P0_5 |
P0_5 |
115200 |
6.4.3.2. JTAG (No Flag Defined)
Uses shared memory for message exchange. The host application reads from and writes to a certain memory region with the JTAG interface. The Flash programmer constantly polls one of these regions for new messages and responds accordingly. There are two regions defined:
BASE_MEMORY - in this region messages and responses are stored
TARGET_MEMORY - in this region the payload is stored
The available message space is limited to 64K for DA1458x and to 32K for DA1453x (the limitations of the actual message headers also apply here. In case of write request, the offset field is 2 bytes wide which covers the first 64K/32K memory addresses).
Note
The message exchange protocol slightly differs in both cases and is described in another section.
6.4.4. Functionality
The Flash programmer supports the following operations:
hardware setup required to operate the FLASH, EEPROM, OTP peripherals (this includes enabling LDO and GPIO configuration)
reading the currently running flash programmer version
reading the requested amount of data from the application memory regions
writing the requested amount of data to the application memory regions
erasing the requested amount of data from the application memory regions (not supported by all non-volatile memory types)
6.4.5. Data Exchange Protocol
Flash programmer listens for host commands in an infinite loop. The host should receive a response for each of the issued actions. Those should be issued sequentially once the previous ones were completed by the target. This message exchange sequence is done differently for each of the supported exchange channels.
6.4.5.1. UART
The host sends a command packet through UART in the following form:
Len (16 bits) |
|
Op Code |
Address (32 bits) |
Length (16 bits) |
Data … |
|---|---|---|---|---|---|
HEADER SECTION |
MESSAGE SECTION |
||||
The first Len parameter is the total length of the message section, which starts with the Op Code (8 bits) and ends where the variable length Data buffer ends. checksum is also calculated for the message section. The message section length is limited by the 2 bytes wide Len.
The result response sent to the host varies from one message to the other. The exact request and response messages are presented later in this document but it is important to note that they do also have the header section that contain the Len and checksum fields.
Data is transferred over the wire with a network byte order (big endian).
6.4.5.2. JTAG (Memory Mapped API)
The host writes a message to the memory section to issue a command, which
starts at the address that is in the BASE_MEMORY variable. The message is structured
in the following form:
Memory offset |
Memory content |
Order |
|---|---|---|
ACTION_OFFSET |
Op Code |
LSB |
SIZE_OFFSET |
Length (16 bits) |
MSB |
SIZE_OFFSET + 1 |
LSB |
|
ADDRESS_OFFSET |
Address Offset (32 bits) |
|
ADDRESS_OFFSET + 1 |
||
ADDRESS_OFFSET + 2 |
MSB |
|
ADDRESS_OFFSET + 3 |
||
RESULT_OFFSET |
Result |
LSB |
ERROR_OFFSET |
Additional error code when Result is not ACTION_OK |
|
ERROR_OFFSET + 1 |
||
ERROR_OFFSET + 2 |
MSB |
|
ERROR_OFFSET + 3 |
Memory offset |
Memory content |
|---|---|
0 |
|
1 |
|
… |
Additionally the payload of Length is written into the Data
buffer pointed by the TARGET_MEMORY variable when applicable.
Note
The host writes the packet sections at certain offsets relative to the starting address that is saved in the BASE_MEMORY variable. Writing the Op Code should be the last step as this triggers the action on the target platform. The Op Code value changes back to 0 once the message is processed and the response in the Result section is filled. This way the host knows when to read the results of the triggered action. Similarly to the messages exchanged via UART the response structure depends on the command sent by the host.
For the DA1453x/DA1458x platform, memory addresses and offsets are set according to the following table:
Platform |
TARGET_MEMORY |
BASE_MEMORY |
ACTION_OFFSET |
SIZE_OFFSET |
ADDRESS_OFFSET |
RESULT_OFFSET |
|---|---|---|---|---|---|---|
DA1458x |
0x07FC8000 |
0x07FC7C00 |
0x00 |
0x02 |
0x04 |
0x08 |
DA1453x |
0x07FC4000 |
0x07FC3C00 |
0x00 |
0x02 |
0x04 |
0x08 |
Because of the nature of the JTAG interface, no endianness conversion is being done. Data should be written in the target platform’s endianness (little endian).
6.4.5.3. Handshake
The host application needs to receive a signal from the target to determine if the target is ready to receive requests. This is done differently for both communication channels:
UART:
Target sends the ‘’Hello’’ string over UART to report readiness.
JTAG:
Target sets the result status value to ACTION_READY at the
BASE_MEMORY + RESULT_OFFSET memory address. The host application can
monitor this memory address to detect flash_programmer readiness.
6.4.5.4. Messages
Note that the following list of messages do not list the header sections (Length, checksum), which is sent along every UART message that is exchanged over the protocol.
6.4.5.4.1. General
- ACTION_READ_VERSION
(0x10) - Reads the flash programmer application version
UART:
Table 49 UART_REQUEST Len
(16 bits)
- checksum
(32 bits)
Op Code
0x07
checksum
0x10
Table 50 UART_RESPONSE Len
(16 bits)
- checksum
(32 bits)
Op Code
0x0D
checksum
0x82
JTAG:
Table 51 Memory Layout at BASE_MEMORY Address Memory offset
Request memory content
Response memory content
ACTION_OFFSET
0x10 (ACTION_READ_VERSION)
0x00 (NO_ACTION)
SIZE_OFFSET
do not care
do not care
ADDRESS_OFFSET
do not care
do not care
RESULT_OFFSET
do not care
0x82 (ACTION_CONTENTS)
Table 52 Data Buffer Memory Layout at TARGET_MEMORY Address Memory offset
Request memory content
Response memory content
0
do not care
v
1
do not care
_
2
do not care
5
…
do not care
…
- ACTION_VPP_ENABLE
(0x50) - Enable the transistor that controls high voltage (6.8v) when OTP memory is written.
UART:
Table 53 UART_REQUEST Len
(16 bits)
- checksum
(32 bits)
Op Code (8 bits)
VPP_ENABLE (8 bits)
0x02
checksum
0x50
0x00 or 0x01
Table 54 UART_RESPONSE Len
(16 bits)
- checksum
(32 bits)
Status (8 bits)
0x01
checksum
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
- ACTION_READY
(0x5A) - This is used only by firmware to inform the host that the target is ready to handle host requests when running in Shared Memory Mode (JTAG).
JTAG:
Table 55 Memory Layout at BASE_MEMORY Address Memory offset
Memory content when not ready
Memory content when ready
ACTION_OFFSET
do not care
do not care
SIZE_OFFSET
do not care
do not care
ADDRESS_OFFSET
do not care
do not care
RESULT_OFFSET
0x00
0x82 (ACTION_READY)
- ACTION_UART_GPIOS
(0x31) - Configure UART data lines. Returns ACTION_ERROR if pins are incorrect.
UART:
Table 56 UART_REQUEST Len (16 bits)
- checksum
(32 bits)
Op Code
TX_PORT
TX_PIN
RX_PORT
RX_PIN
0x05
checksum
0x31
0x00
0x04
0x00
0x05
Table 57 UART_RESPONSE Len (16 bits)
- checksum
(32 bits)
Status (8 bits)
0x01
checksum
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
JTAG:
Unsupported
6.4.5.4.2. OTP Memory
- ACTION_OTP_READ
(0x80) - Read the requested amount of data from the OTP memory at the given offset.
UART:
Table 58 UART_REQUEST Len (16 bits)
- checksum
(32 bits)
Op Code
Address offset (32 bits)
Length (16 bits)
Len (16 bits)
checksum (32 bits)
0x07 + length
checksum
0x80
offset
length
0x07 + length
checksum
Table 59 UART_RESPONSE Len
(16 bits)
- checksum
(32 bits)
Status(8 bits)
Data …
0x01 + data length
checksum
0x82 (ACTION_CONTENTS)
read data
JTAG:
Table 60 Memory Layout at BASE_MEMORY Address Memory offset
Request memory content
Response memory content
ACTION_OFFSET
0x80 (ACTION_OTP_READ)
0x00 (NO_ACTION)
SIZE_OFFSET
data length
data length
ADDRESS_OFFSET
address offset
address offset
RESULT_OFFSET
do not care
0x82 (ACTION_CONTENTS)
Table 61 Data Buffer Memory Layout at TARGET_MEMORY Address Memory offset
Request memory content
Response memory content
0
do not care
data0
1
do not care
data1
2
do not care
data2
…
do not care
data3
- ACTION_OTP_WRITE
(0x81) - Write the requested amount of data into the OTP memory at the given offset.
UART:
Table 62 UART_REQUEST Len (16 bits)
- checksum
(32 bits)
Op Code
Address offset (32 bits)
Length (16 bits)
Data (LENGTH*8 bits)
0x07 + length
checksum
0x81
memory address
length
data to write
Table 63 UART_RESPONSE Len
(16 bits)
- checksum
(32 bits)
Status (8 bits)
Error Code (32 bits)
0x01 or 0x05
checksum
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
Additional error code - only if Status is set to ACTION_ERROR.
JTAG:
Table 64 Memory Layout at BASE_MEMORY Address Memory offset
Request memory content
Response memory content
ACTION_OFFSET
0x81 (ACTION_OTP_WRITE)
0x00 (NO_ACTION)
SIZE_OFFSET
size
size
ADDRESS_OFFSET
address offset
address offset
RESULT_OFFSET
do not care
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
ERROR_OFFSET
do not care
Error code (32 bits) - only if result is ACTION_ERROR
Table 65 Data Buffer Memory Layout at TARGET_MEMORY Address Memory offset
Request memory content
Response memory content
0
data0
data0
1
data1
data1
2
data2
data2
…
data3
data3
6.4.5.4.3. SPI FLASH
- ACTION_SPI_READ
(0x90) - Read the requested amount of data from the SPI FLASH memory at given memory address.
UART:
Table 66 UART_REQUEST Len (16 bits)
- checksum
(32 bits)
Op Code
Address offset (32 bits)
Length (16 bits)
Data (LENGTH*8 bits)
0x07 + length
checksum
0x90
memory address
length
data to write
Table 67 UART_RESPONSE Len (16 bits)
- checksum
(32 bits)
Status (8 bits)
Data…
0x01 + data length
checksum
0x82 (ACTION_CONTENTS)
read data
JTAG:
Table 68 Memory Layout at BASE_MEMORY Address Memory offset
Request memory content
Response memory content
ACTION_OFFSET
0x90 (ACTION_SPI_READ)
0x00 (NO_ACTION)
SIZE_OFFSET
data length
data length
ADDRESS_OFFSET
address
address
RESULT_OFFSET
do not care
0x82 (ACTION_CONTENTS)
Table 69 Data Buffer Memory Layout at TARGET_MEMORY Address Memory offset
Request memory content
Response memory content
0
do not care | data0
1
do not care | data1
2
do not care | data2
…
do not care | data3
- ACTION_SPI_WRITE
(0x91) - Write the requested amount of data into SPI FLASH memory at given offset.
UART:
Table 70 UART_REQUEST Len (16 bits)
- checksum
(32 bits)
Op Code
Address offset (32 bits)
Length (16 bits)
Data (LENGTH*8 bits)
0x07 + length
checksum
0x91
memory address
length
data to write
Table 71 UART_RESPONSE Len
(16 bits)
- checksum
(32 bits)
Status (8 bits)
Error Code (32 bits)
0x01 or 0x05
checksum
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
Additional error code - only if Status is set to ACTION_ERROR.
JTAG:
Table 72 Memory Layout at BASE_MEMORY Address Memory offset
Request memory content
Response memory content
ACTION_OFFSET
0x91 (ACTION_FLASH_WRITE)
0x00 (NO_ACTION)
SIZE_OFFSET
size
size
ADDRESS_OFFSET
memory address
memory address
RESULT_OFFSET
do not care
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
ERROR_OFFSET
do not care
Error code (32 bits) - only if result is ACTION_ERROR
Table 73 Data Buffer Memory Layout at TARGET_MEMORY Address Memory offset
Request memory content
Response memory content
0
data0
data0
1
data1
data1
2
data2
data2
…
data3
data3
- ACTION_SPI_ERASE
(0x92) - Erase SPI FLASH memory.
UART:
Table 74 UART_REQUEST Len (16 bits)
- checksum
(32 bits)
Op Code
0x01
checksum
0x92
Table 75 UART_RESPONSE Status (8 bits)
Error Code (32 bits)
Status (8 bits)
Error Code (32 bits)
0x01 or 0x05
checksum
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
Additional error code - only if Status is set to ACTION_ERROR.
JTAG:
Table 76 Memory Layout at BASE_MEMORY Address Memory offset
Request memory content
Response memory content
ACTION_OFFSET
0x92 (ACTION_SPI_ERASE)
0x00 (NO_ACTION)
SIZE_OFFSET
Do not care
Do not care
ADDRESS_OFFSET
Do not care
Do not care
RESULT_OFFSET
Do not care
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
ERROR_OFFSET
Do not care
Error code (32bits) - only if result is ACTION_ERROR
Note
Data buffer memory layout at TARGET_MEMORY address: Target memory is not used.
- ACTION_SPI_ID
(0x93) - Read flash JEDEC ID.
UART:
Table 77 UART_REQUEST Len (16 bits)
- checksum
(32 bits)
Op Code
0x01
checksum
0x93
Table 78 UART_RESPONSE Len (16 bits)
checksum (32bits)
Status (8 bits)
MANUFACTURER ID (8 bits)
JEDEC ID 1 (8 bits)
0x05
checksum
0x82 (ACTION_CONTENTS)
id
id
JTAG:
Table 79 Memory Layout at BASE_MEMORY Address Memory offset
Request memory content
Response memory content
ACTION_OFFSET
0x93 (ACTION_EEPROM_READ)
0x00 (NO_ACTION)
SIZE_OFFSET
Do not care
Do not care
ADDRESS_OFFSET
Do not care
Do not care
RESULT_OFFSET
Do not care
0x82 (ACTION_CONTENTS)
Table 80 Data Buffer Memory Layout at TARGET_MEMORY Address Memory offset
Request memory content
Response memory content
0
Do not care
Device ID byte 2
1
Do not care
Device ID byte 1
2
Do not care
Manufacturer ID
3
Do not care
0
- ACTION_SPI_ERASE_BLOCK
(0x94) - Erase specified number of sectors starting from flash address.
UART:
Table 81 UART_REQUEST Len (16 bits)
- checksum
(32 bits)
Op Code
Address (32 bits)
Sectors (16 bits)
0x07
checksum
0x94
address
n
Table 82 UART_RESPONSE Len (16 bits) - checksum (32bits) - Status (8 bits) - Additional error code (only if Status is not ACTION_OK) - MANUFACTURER ID (8 bits) - JEDEC ID 1 (8 bits)
0x01 or 0x05 - checksum - 0x83 (ACTION_OK) or 0x84 (ACTION_ERROR) - Additional error code - 0x01 or 0x05 - checksum
JTAG:
Table 83 Memory Layout at BASE_MEMORY Address Memory offset
Request memory content
Response memory content
ACTION_OFFSET
0x94 (ACTION_SPI_ERASE_BLO CK)
0x00 (NO_ACTION)
SIZE_OFFSET
sector count
Do not care
ADDRESS_OFFSET
address
Do not care
RESULT_OFFSET
Do not care
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
ERROR_OFFSET
Do not care
Error code - only if result is ACTION_ERROR
Note
Data buffer memory layout at TARGET_MEMORY address: Target memory is not used.
- ACTION_SPI_GPIOS
(0x95) - Configure SPI data lines. Returns ACTION_ERROR if any pin is incorrect.
UART:
Table 84 UART_REQUEST Len (16 bits)
- checksum
(32 bits)
Op Code
CS PORT
CS PIN
CLK PORT
CLK PIN
DO PORT
DO PIN
DI PORT
DI PIN
0x09
checksum
0x95
0x00
0x03
0x00
0x00
0x00
0x06
0x00
0x05
Table 85 UART_RESPONSE Len (16 bits)
- checksum
(32 bits)
Status
0x01
checksum
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
JTAG:
Table 86 Memory Layout at BASE_MEMORY Address Memory offset
Request memory content
Response memory content
ACTION_OFFSET
0x95 (ACTION_SPI_GPIOS)
0x00 (NO_ACTION)
SIZE_OFFSET
Do not care
Do not care
ADDRESS_OFFSET
Do not care
Do not care
RESULT_OFFSET
Do not care
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
Table 87 Data Buffer Memory Layout at TARGET_MEMORY Address Memory offset
Request memory content
Response memory content
0
0x00 (CS PORT)
Do not care
1
0x03 (CS PIN)
Do not care
2
0x00 (SCL PORT)
Do not care
3
0x00 (SCL PIN)
Do not care
4
0x00 (DO PORT)
Do not care
5
0x06 (DO PIN)
Do not care
6
0x00 (DI PORT)
Do not care
- ACTION_SPI_HEADER
(0x96) - Write image header to SPI flash.
UART:
Table 88 UART_REQUEST Len (16 bits)
checksum (32 bits)
Op Code
Size (24 bits)
0x04
checksum
0x96
0x012345
Table 89 UART_RESPONSE Len (16 bits)
- checksum
(32 bits)
Status
0x01
checksum
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
JTAG:
Table 90 Memory Layout at BASE_MEMORY Address Memory offset
Request memory content
Response memory content
ACTION_OFFSET
0x96 (ACTION_SPI_HEADER)
0x00 (NO_ACTION)
SIZE_OFFSET
Do not care
Do not care
ADDRESS_OFFSET
Do not care
Do not care
RESULT_OFFSET
Do not care
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
Table 91 Data Buffer Memory Layout at TARGET_MEMORY Address Memory offset
Request memory content
Response memory content
0
0x45 (Size LSB)
Do not care
1
0x23
Do not care
2
0x01 (Size MSB)
Do not care
3
Do not care
Do not care
6.4.5.4.4. I2C EEPROM
- ACTION_EEPROM_READ
(0xA0) - Read n bytes of data from specified address in I2C EEPROM.
UART:
Table 92 UART_REQUEST Len (16 bits)
- checksum
(32 bits)
Op Code
Address (32 bits)
Size (16 bits)
0x07
checksum
0xA0
address
n
Table 93 UART_RESPONSE Len
(16 bits)
- checksum
(32 bits)
Status
(8 bits)
Data
…
0x01 + data length
checksum
0x82 (ACTION_CONTENTS)
read data
JTAG:
Table 94 Memory Layout at BASE_MEMORY Address Memory offset
Request memory content
Response memory content
ACTION_OFFSET
0xA0 (ACTION_EEPROM_READ)
0x00 (NO_ACTION)
SIZE_OFFSET
n
Do not care
ADDRESS_OFFSET
address
Do not care
RESULT_OFFSET
Do not care
0x82 (ACTION_CONTENTS)
Table 95 Data buffer Memory Layout at TARGET_MEMORY Address Memory offset
Request memory content
Response memory content
0
Do not care
data byte 1
1
Do not care
data byte 2
…
Do not care
n-1
Do not care
data byte n
- ACTION_EEPROM_WRITE
(0xA1) - Write n bytes of data to specified address in I2C EEPROM.
UART:
Table 96 UART_REQUEST Len (16 bits)
- checksum
(32 bits)
Op Code
Address offset (32 bits)
Length (16 bits)
Data (LENGTH*8 bits)
0x07 + length
checksum
0xA1
memory address
length
data to write
Table 97 UART_RESPONSE Len (16 bits)
- checksum
(32 bits)
Status
0x01
checksum
0x83 (ACTION_OK)
Or
Table 98 UART_RESPONSE Len (16 bits)
- checksum
(32 bits)
Status
Error code (32 bits)
0x05
checksum
0x84 (ACTION_ERROR)
error code
JTAG:
Table 99 Memory Layout at BASE_MEMORY Address Memory offset
Request memory content
Response memory content
ACTION_OFFSET
0xA1 (ACTION_EEPROM_WRITE)
0x00 (NO_ACTION)
SIZE_OFFSET
n
Do not care
ADDRESS_OFFSET
address
Do not care
RESULT_OFFSET
Do not care
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
ERROR_OFFSET
Do not care
Error code
Table 100 Data Buffer Memory Layout at TARGET_MEMORY Address Memory offset
Request memory content
Response memory content
0
data byte 1
Do not care
1
data byte 2
Do not care
…
Do not care
n-1
data byte n
Do not care
- ACTION_I2C_GPIOS
(0xA3) - Configure I2C data lines. Returns ACTION_ERROR if pins are incorrect.
UART:
Table 101 UART_REQUEST - Len (16 bits)
(32 bits)
checksum
Op Code
Address offset (32 bits)
Length (16 bits)
Data (LENGTH*8 bits)
0x07 + length
checksum
0xA3
memory address
length
data to write
Table 102 UART_RESPONSE Len (16 bits)
- checksum
(32 bits)
Status
0x01
checksum
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
JTAG:
Table 103 Memory Layout at BASE_MEMORY Address Memory offset
Request memory content
Response memory content
ACTION_OFFSET
0xA3 (ACTION_I2C_GPIOS)
0x00 (NO_ACTION)
SIZE_OFFSET
Do not care
Do not care
ADDRESS_OFFSET
Do not care
Do not care
RESULT_OFFSET
Do not care
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
ACTION_OFFSET
0xA3 (ACTION_I2C_GPIOS)
0x00 (NO_ACTION)
Table 104 Data Buffer Memory Layout at TARGET_MEMORY Address Memory offset
Request memory content
Response memory content
0
0x00 (SCL PORT)
Do not care
1
0x04 (SCL_PIN)
Do not care
2
0x00 (SDA_PORT)
Do not care
3
0x05 (SDA_PIN)
Do not care
- ACTION_I2C_HEADER
(0xA4) - Write image header to I2C EEPROM.
UART:
Table 105 UART_REQUEST Len (16 bits)
- checksum
(32 bits)
Op Code
Size (24 bits)
0x07 + length
checksum
0xA4
memory address
Table 106 UART_RESPONSE Len (16 bits)
- checksum
(32 bits)
Status
0x01
checksum
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
JTAG:
Table 107 Memory Layout at BASE_MEMORY Address Memory offset
Request memory content
Response memory content
ACTION_OFFSET
0xA4 (ACTION_I2C_HEADER)
0x00 (NO_ACTION)
SIZE_OFFSET
Do not care
Do not care
ADDRESS_OFFSET
Do not care
Do not care
RESULT_OFFSET
Do not care
0x83 (ACTION_OK) or 0x84 (ACTION_ERROR)
Table 108 Data Buffer Memory Layout at TARGET_MEMORY Address Memory offset
Request memory content
Response memory content
0
0x45 (Size LSB)
Do not care
1
0x23
Do not care
2
0x01 (Size MSB)
Do not care
3
Do not care
Do not care
6.4.5.4.5. Response Status
The following codes are used to communicate the result of actions triggered by the host.
- ACTION_CONTENTS
(0x82) - Common status when data is returned.
- ACTION_OK
(0x83) - Common success status.
- ACTION_ERROR
(0x84) - Common error status.
- ACTION_DATA
(0x85) - Not used.
- ACTION_INVALID_COMMAND
(0x86) - Sent to the host when target receives unknown command.
- ACTION_INVALID_CRC
(0x87) - Can be sent as a response to any request over UART if checksum does not match the message content.