6.1. Booting from Serial Interfaces

The DA1453x/DA1458x can boot from external serial devices when the OTP memory is not programmed. This is to enable the development of application code. At power-up the system enters Development Mode, where the boot code decides which interface to boot from. This section describes the boot sequence for all supported serial interfaces and provides the developer with the necessary information to realize the protocol required to establish communication between an external device and the DA1453x/DA1458x.

Note

For more information about booting the DA1453x/DA1458x, see the respective datasheets.

6.1.1. Introduction

The DA1453x/DA1458x operates in two modes: Normal mode and Development mode. The decision which mode the chip enters after power-up, is taken by the boot code that resides in the ROM. A complete flow chart of the boot code is illustrated in:

The boot ROM code reads the Application Programmed flags from the OTP header to identify whether the chip is in Development mode or Normal mode.

Note

  • DA1458x: The OTP memory contains all zeros if not programmed.

  • DA1453x: The OTP memory contains all ones if not programmed.

If the predefined value is identified, then this ensures that the OTP memory is functional and that the application code is programmed. However, if the predefined value is not identified, either the OTP memory is not programmed (blank) or is not operational (random data).

When in Development mode, the boot ROM code initializes all serial peripheral devices from which the DA1453x/DA1458x might download code. The options are:

  • UART

  • SPI (both master and slave)

  • I2C (only master)

The boot ROM code searches for a valid response on various combinations of I/Os one after the other. There is also the option that the user can define desired I/Os with the use of a specific OTP field for the SPI interface.

The boot pins and serial peripherals search sequence are presented in the following section.

6.1.2. Boot Pins and Serial Peripherals Search Sequence

The DA1453x/DA1458x boot pins and serial peripherals search sequence are presented in Table 19, Table 20 and Table 21 Table 22

Table 19 DA1458x Development Mode Peripheral Pin Mapping

Interface

Signal

Step A

Step B

Step C

Step D

SPI Master

SCK

P0_0

P0_0

CS

P0_3

P0_1

MISO

P0_6

P0_2

MOSI

P0_5

P0_3

UART

TX

P0_0

P0_2

P0_4

P0_6

RX

P0_1

P0_3

P0_5

P0_7

Baud Rate

57600 / 8-N-1

115200 / 8-N-1

57600 / 8-N-1

9600 / 8-N-1

SPI Slave

SCK

P0_0

CS

P0_3

MOSI

P0_6

MISO

P0_5

I2C

SCL

P0_0

P0_2

P0_4

P0_6

SDA

P0_1

P0_3

P0_5

P0_7

Table 20 DA1458x Development Mode Peripheral Search Sequence

Sequence

Action

0

SPI Master Step A

1

SPI Master Step B

2

UART Step A

3

UART Step B

4

UART Step C

5

UART Step D

6

SPI Slave Step A

7

I2C Step A

8

I2C Step B

9

I2C Step C

10

I2C Step D

Table 21 DA14531-00, DA14531-01 and DA14530 Boot Sequence Steps

Step 1: Boot from external SPI master

Step 2: Boot from 1-wire UART (first option)

Step 3: Boot from 1-wire UART (second option)

Step 4: Boot from 2-wire UART

Step 5: Boot from external SPI slave

Step 6: Boot from I2C

P0_0/RST

MISO

Tx

MOSI

P0_1

MOSI

Rx

SCS

P0_2

P0_3

SCS

RxTx

MISO

SDA

P0_4

SCK

SCK

SCL

P0_5

RxTx (default)

P0_6

P0_7

P0_8

P0_9

P0_10

P0_11
Table 22 DA14535 Boot Sequence Steps

Step 1: Boot from external SPI master

Step 2: Boot from 1-wire UART (first option)

Step 3: Boot from 1-wire UART (second option)

Step 4: Boot from 2-wire UART

Step 5: Boot from 2-wire UART

Step 6: Boot from external SPI slave

Step 7: Boot from I2C

P0_0/RST

MISO

Tx

MOSI

P0_1

MOSI

Tx

Rx

SCS

P0_2

P0_3

SCS

RxTx

Rx

MISO

SDA

P0_4

SCK

SCK

SCL

P0_5

RxTx (default)

P0_6

P0_7

P0_8

P0_9

P0_10

P0_11

At each step, the boot ROM code sends a certain character to the peripheral controller and waits for an answer. If no answer is received within a certain amount of time, a timeout instructs the code to continue to the next step. If a response is detected, a specific protocol is executed and communication between the DA1453x/DA1458x and the external serial device is established. The code is downloaded from the external serial device to DA1453x/DA1458x RAM.

6.1.3. Boot Sequence

The boot sequence of DA14585 is shown in Figure 78.

../_images/booting-image1.png

Figure 78 DA14585 Boot Sequence

The boot sequence of DA14586 is shown in Figure 79.

../_images/booting-image2.png

Figure 79 DA14586 Boot Sequence

The boot sequence of DA14531-00, DA14531-01 and DA14530 booting is shown in Figure 80.

../_images/booting-image3.png

Figure 80 DA14531-00, DA14531-01 and DA14530 Boot Sequence

The boot sequence of DA14535 is shown in Figure 81.

../_images/booting-image4.png

Figure 81 DA14535 Boot Sequence

6.1.4. DA1453x/DA1458x Boot Protocols

6.1.4.1. Boot from SPI Bus - DA1453x/DA1458x Act as SPI Slave

The boot ROM code initially configures the DA1453x/DA1458x SPI controller with the following parameters:

  • 8 bit mode

  • Slave role

  • Mode 0: SPI clock is initially expected to be low and SPI phase is zero.

The protocol required to establish a successful communication and to download the SW into the RAM is given in Table 23.

Note

The master SPI device generates the SPI clock for the DA1458x. In case of a continuous SPI clock, the frequency of this clock must not be higher than 500 kHz. For an SPI clock frequency higher than 500 kHz, the SPI clock should be paused after each byte.

Table 23 Boot Protocol - DA1453x/DA1458x as SPI Slave

Byte nr.

DA1453x/DA1458x MOSI

DA1453x/DA1458x MISO

0

Preamble: 0x70

1

Preamble: 0x50

2

Empty: 0x00

3

Length LS byte

Preamble ACK: 0x02

Preamble NACK:0x20

4

Length MS byte

5

checksum byte

6

Mode byte

Length ACK:0x02

Length NACK:0x20

7

Empty: 0x00

8

Data bytes

Code/Mode ACK:0x02

Code/Mode NACK:0x20

The external SPI master device starts by sending the Preamble bytes (0x70 and 0x50) followed by a zero byte. The DA1453x/DA1458x confirms the reception of the Preamble with 0x02 (Acknowledged) or 0x20 (Not Acknowledged) in case something went wrong. Bytes 3 and 4 define the length of the payload to follow. The least significant byte is sent first. The length is a number that represents the amount of data in 32-bit words.

Next, the SPI master must send the calculated checksum of the payload. The checksum is calculated by XORing every successive byte with the previous value. Initial checksum value is 0xFF.

Byte 6 defines the mode of operation directed by the SPI master (8, 16 or 32-bit modes) while the DA1453x/DA1458x SPI slave answers with ACK/NACK regarding the reception of the length bytes. The mode is encoded as follows:

  • 0x00 = 8-bit mode

  • 0x01 = 16-bit mode

  • 0x02 = 32-bit mode

  • 0x03 = Reserved

Byte 8 is the last control byte, where DA1453x/DA1458x replies with ACK/NACK with regard to the reception of the checksum and the mode, while the external SPI master starts to send the first byte of the payload (least significant byte of the first word).

The data section is presented in Table 24, and takes into consideration the instructed mode. The stream of data is followed by 2 extra empty slots to provide the required time to the DA1453x/DA1458x SPI controller to compute the checksum and answer with ACK/NACK.

Upon completion of the SPI master process, all related pads are set to input and pulled down.

Table 24 SPI Master Data Communication

Slot nr.

MOSI (8-bit mode)

MOSI (16-bit mode)

MOSI (32-bit mode)

MISO

0

byte 0

byte 1, byte 0

byte 3, byte 2, byte 1, byte 0

1

byte 1

byte 3, byte 2

byte 7, byte 6, byte 5, byte 4

…

4*Len-1 or

2*Len-1 or

Len-1

byte (4*Len–1)

16-bit word (2*Len-1)

32-bit word (Len-1)

all 0x00

all 0x00

all 0x00

all 0xAA

all 0x00

all 0x00

all 0x00

ACK: 0x02

NACK: 0x20

6.1.4.2. Booting from UART

The boot ROM code initially configures the DA1453x/DA1458x UART controller with the following parameters:

  • Bits: 8

  • No parity

  • 1 stop bit

  • Baud rate: fixed at 115.2 Kbps for DA1453x, variable for DA1458x (see Table 19).

The protocol required to establish successful communication and to download the SW image into the RAM is shown in the next tables depending on the chip:

  • DA1458x

    Table 25 Boot Protocol

    Byte nr.

    DA1458x TX

    DA1458x RX

    0

    STX = 0x02

    1

    SOH = 0x01

    2

    LEN_LSB byte (Basic)

    3

    LEN_MSB byte (Basic)

    4

    LEN_LSB byte (Extended)

    5

    LEN_MSB byte (Extended)

    6

    ACK = 0x06 or NACK = 0x15

    7 to N

    SW code bytes

    N+1

    checksum

    N+2

    ACK = 0x06

    1. The protocol starts with the DA1458x UART TX pin that transmits 0x02 (Start TX - STX).

    2. The external device is expected to answer with a 0x01 (Start of Header - SOH).

      1. If the Basic LEN_LSB and LEN_MSB bytes are both zero, then the SW image is equal to or over 64 KByte. The following two Extended LEN_LSB and LEN_MSB bytes define the additional image length over the 64 KByte boundary. In that case the length of the downloaded SW image is calculated by the following formula:

        • length = 64 KByte + additional length defined by Extended LEN_MSB and LEN_LSB bytes.

        The DA1458x answers with 0x06 (ACK) if the 5 bytes have been received and SOH has been identified, or answers with 0x15 (NACK) if anything went wrong.

      2. If at least one of the Basic LEN_LSB or LEN_MSB byte is NOT zero, then the SW image is lower than 64 KByte. These bytes define the length of the downloaded SW image.

        The DA1458x answers with 0x06 (ACK) if the 3 bytes have been received and SOH has been identified, or answers with 0x15 (NACK) if anything went wrong.

  • DA1453x

    Table 26 Boot Protocol

    Byte nr.

    DA1453x TX

    DA1453x RX

    0

    STX = 0x02

    1

    SOH = 0x01

    2

    LEN_LSB byte

    3

    LEN_MSB byte

    4

    ACK = 0x06 or NACK = 0x15

    5 to N

    SW code bytes

    N+1

    checksum

    N+2

    ACK = 0x06

    The protocol starts with the DA1453x UART TX pin that transmits 0x02 (Start TX - STX). The external device is expected to answer with a 0x01 (Start of Header - SOH) byte followed by 2 more bytes (LEN_LSB, LEN_MSB), which define the length of the code to be downloaded (first byte is the least significant, second the most significant). The DA1453x answers with 0x06 (ACK) if the 3 bytes have been received and SOH has been identified, or answers with 0x15 (NACK) if anything went wrong.

At this point the connection has been successfully established and the SW code will start to be downloaded. The next N bytes are received and put into the RAM, and starts at address 0x07FC0000 as shown in Table 27.

Table 27 RAM Word Alignment

Address

Byte 3 (MSB)

Byte 2

Byte 1

Byte 0 (LSB)

0x07FC0000

Code byte 3

Code byte 2

Code byte 1

Code byte 0

0x07FC0004

…

…

Code byte 5

Code byte 4

Upon completion of the required code bytes, the boot code calculates the checksum and send it over the URX. The boot sequence ends when the value 0x06 (ACK) is read at the URX line. checksum is calculated by XORing every successive byte with the previous value. The initial checksum value is 0x00.

At the final step of the boot code, the SYS_CTRL_REG register is programmed to:

  • Remap to address zero for execution to RAM (SYS_CTRL_REG[REMAP_ADR0] = 0x2)

  • Apply a SW reset, so the system starts to execute code at the remapped address (SYS_CTRL_REG[SW_RESET] = 0x1)

6.1.4.3. Booting from SPI Bus - DA1453x/DA1458x acting as SPI Master

The boot code configures the SPI with the following parameters:

  • 8 bit mode

  • Master role

  • Mode 3: SPI clock is initially high and SPI phase is shifted by 90 degrees.

  • The SPI clock frequency is set by default at 2 MHz.

The protocol required to establish a successful communication and to download the SW image into the RAM is shown in the next tables, and depend on the chip:

  • DA1458x as SPI master

    Table 28 Boot Protocol

    Byte nr.

    DA1458x MOSI

    DA1458x MISO

    0

    Read command

    1

    Address byte 0 = 0x00

    2

    Address byte 1 = 0x00

    3 to N

    Dummy bytes = 0x00

    N+1

    ‘p’ = 0x70

    N+2

    ‘P’ = 0x50

    N+3 to N+5

    Dummy bytes

    N+6

    Length extension byte

    N+7

    LEN_MSB byte

    N+8

    LEN_LSB byte

    N+9 …

    Code bytes

    1. If Length Extension byte is equal to one, then the SW downloaded image size will be equal to or over 64 KByte. The image length is calculated based on the following formula:

      • length = 64 KByte + additional length defined by LEN_MSB and LEN_LSB bytes.

    2. If Length Extension byte is NOT equal to one, then the SW downloaded image size will be lower than 64 KByte. The image length is defined by the LEN_MSB and LEN_LSB bytes.

  • DA1453x as SPI master

    Table 29 Boot Protocol

    Byte nr.

    DA1453x/DA1458x MOSI

    DA1453x/DA1458x MISO

    0

    Read command

    1

    Address byte 0 = 0x00

    2

    Address byte 1 = 0x00

    3 to N

    Dummy bytes = 0x00

    N+1

    ‘p’ = 0x70

    N+2

    ‘P’ = 0x50

    N+3 to N+6

    Dummy bytes

    N+7

    LEN_MSB byte

    N+8

    LEN_LSB byte

    N+9 …

    Code bytes

The image length is defined by the LEN_MSB and LEN_LSB bytes.

The sequence as described in Table 28 or Table 29 is repeated for 4 different cases regarding the Read command and the Dummy byte parameters as indicated in Table 30.

Table 30 SPI Read and Dummy Byte Cases

Case nr.

Read command opcode

Number of dummy bytes

0

0x03

0

1

0x03

1

2

0x0B

2

3

0xE8

5

Note

The length of the SW image is received after the 4th Read command is issued (opcode = 0xE8).

As soon as the length has been received (2 bytes - LEN_MSB and LEN_LSB), the actual code download into RAM starts. The start address is the base address of the RAM. The byte alignment is according to Table 27.

During the final step of the boot code a SW reset is given and the system starts to execute the downloaded code.

6.1.4.4. Booting from I2C Bus - DA1453x/DA1458x Acting as I2C Master

The boot code initializes the I2C controller in master mode with the following parameters:

  • I2C slave address = 0x50 (7-bit address)

  • I2C speed to standard mode (100 kbit/s)

The boot code initially scans to find an I2C slave device at addresses 0x50 up to 0x57. After a successful slave address identification, a specific protocol is executed to download the SW into the RAM as shown in the next tables. There is a specific table per chip. If unsuccessful, a timeout is programmed to expire after 20 ms to get the chip out of the I2C booting mode and into the next one.

  • DA1458x as I2C master

    Table 31 Boot Protocol - DA1458x as I2C master

    Byte nr.

    DA1458x SDA

    Action (DA1458x I2C master)

    0

    0x70

    Read command

    1

    0x50

    Read command

    2

    LEN_MSB byte (Basic)

    3

    LEN_LSB byte (Basic)

    4

    checksum over code only (image < 64KByte)

    Read command

    5

    LEN_MSB byte (Extended)

    6

    LEN_LSB byte (Extended)

    7

    checksum over code only (image >= 64KByte)

    Read command

    8 to 31

    Dummy

    Read command

    32 to Length+32

    Code data

    Read command

    1. If the Basic LEN_LSB and LEN_MSB bytes are both zero, then the SW image is equal to or over 64 KByte. The following two Extended LEN_LSB and LEN_MSB bytes define the additional image length over the 64 KByte boundary. In that case the length of the downloaded SW image is calculated by the following formula:

      • length = 64KByte + additional length defined by Extended LEN_MSB and LEN_LSB bytes.

      Byte-4 shall be 1. Byte-7 includes the checksum byte (calculated over code only).

    2. If at least one of the Basic LEN_LSB or LEN_MSB byte is NOT zero, then the SW image is lower than 64 KByte. These bytes define the length of the downloaded SW image.

      Byte-4 includes the checksum byte (calculated over code only).

  • DA1453x as I2C master

    Table 32 Boot Protocol - DA1453x as I2C master

    Byte nr.

    DA1453x SDA

    Action ( DA1453x I2C master)

    0

    0x70

    Read command

    1

    0x50

    Read command

    2

    LEN_MSB byte

    Read command

    3

    LEN_LSB byte

    Read command

    4
    checksum over code

    only

    Read command

    5 to 31

    Dummy

    Read command

    32 to Length+32

    Code data

    Read command

The boot code will calculate the checksum by XORing every successive byte with the previous value. Initial checksum value is 0x00. The checksum is calculated on multiples of 32 bytes. Padding with zeros is required when the payload size is not a multiple of 32 bytes.

At the final step of the boot code a SW reset is given and the system starts to execute the downloaded code.