5. Introduction

DA1470x contains three CPUs: SysCPU(CM33), CMAC (CM0+) and SNC (CM0+) and a RAM pool of 1.5 MB, which can be accessed by all CPUs and the General-Purpose DMA Controller. This access is achieved through the RAM Controller, which implements an intelligent addressing scheme, so that RAM is not fragmented by various data or code allocations, while at the same time allowing for parallel access of multiple data streams on different RAM cells transparently to the application software. This means that all three CPUs and the General-Purpose DMA Controller can access the RAM at the same time.

Besides RAM, the system includes an OQSPI XIP Flash that is also used for code execution and storage of constant data. All projects running on the DA1470x are responsible for the configuration and the usage of the system’s resources.

The application code and data must be organized to be placed and executed in specific aeras in SysRAM and OQSPI flash memory. The user can make changes to this organization to achieve the desired configuration. The RAM controller can run in parallel data flows from/to various masters and each RAM cell can have its own programmable priority scheme. In order to avoid fragmentation, flexible memory allocation per master is supported. Moreover, arbitration is used when two or more masters need to access the same RAM cell, but the address range is different for each master. Finally, there are two cells, RAM9 and RAM10, for CMAC code and data, which runs at the CMAC clock frequency, not the system one.