2. Sleep modes overview
To give an overview of the sleep modes available, the following section will give more idea on each mode and its application.
The block diagram of the DA14531 is as shown below and the highlighted red box is where the retention memory blocks are placed and this includes SysRAM1 (16kB), SysRAM2 (12kB) and SysRAM3 (20kB). So a total of 48kB system RAM is available.
Figure 1 DA14531 Block Diagram
DA14535 in the newer member of DA1453x family which includes two SysRAMs each with 32kB of memory (64kB in total).
Figure 2 DA14535 Block Diagram
The DA14585 block diagram is as shown below with the highlighted red box indicating the retention memory blocks. In total there is 96kB system RAM available, divided in 4 RAM blocks - SysRAM1 (32kB), SysRAM2 (16kB), SysRAM3 (16kB) and SysRAM4 (32kB).
Figure 3 DA14585 Block Diagram
- Extended Sleep mode:
In Extended sleep mode, the system domain except the SysRAM, the radio domain and the peripheral domain are powered down and the XTAL16M clock is stopped. The SysRAM is still powered to retain data but is not accessible.
Supply power to the blocks that facilitate system awakening, including the wakeup timer, quadrature decoder, and BLE timer.
Keeping a Bluetooth® LE connection alive (stack variables or Bluetooth® LE data).
Potentially keep the application code and it can be omitted if the OTP or external Flash is instructed to automatically get mirrored into RAM upon every wake up.
- Deep sleep mode:
In Deep sleep mode, to reduce the power consumption even further, the SysRAM is also powered off optionally retained(typically only SysRAM1 is retained). The status of the other power domains is the same as in Extended sleep mode.
The device can wake-up from deep sleep either using clocked-wake up controller, from GPIOs, RTC alarm (ONLY on DA1453x) or Timer1 (ONLY on DA1453x).
- Hibernation sleep mode (ONLY on DA1453x):
No clock is running. In Hibernation mode as compared to previous two sleep modes, the PD_SLP (Sleep power domain) domain is switched off. This means the CRG (Clock and Reset Generator) is powered off and this is why this mode is called Clock-less mode.
RAM retainability is programmable.
The device is capable of waking up exclusively from GPIOs that have been configured for this purpose. The designated GPIOs for waking the device from hibernation are P0_1 to P0_5.
3. Sleep modes hardware overview (DA1453x)
This section explains the hardware power domains and how these are configured in each of the sleep modes. The sleep mode in general has no power gating programmed. The ARM CPU is idle and waiting for an interrupt, PD_SYS is on , whereas PD_TIM and PD_RAD depend on the programmed enabled value.
To know which power domain powers what part of the blocks, refer to the below figures on mapping of digital power domains and blocks in DA14531 and DA14535:
System Power Domain.
As can be seen, the PD_SYS powers up the SysRAM blocks as seen in the figures below.
Figure 4 DA14531 Mapping of Digital Power Domains and Blocks
Figure 5 DA14535 Mapping of Digital Power Domains and Blocks
Description of the power domain
Table 1 DA1453x Power Domains Description Domain Name
Description
PD_AON
Always powered domain. It contains a Clock-less Wake Up controller and the pad-ring.
PD_SLP
Sleep power domain. It comprises of the ARM/WIC (Wake-up Interrupt controller, the BLE Timer, the PMU/CRG, the Clocked Wakeup Controller, the Quadrature Decoder, and various registers required for the Wake-Up sequence.
PD_SYS
System Power Domain. It comprises of the AHB bus, the OTP cell and controllers, the ROM, the System RAM, the Watchdog, the SW Timer, and the GPIO port multiplexing.
PD_TIM
Timer Power Domain. It comprises of the RTC and the Timer1. These two blocks can be active during the sleep modes.
PD_RAD
Radio Power Domain. It comprises of the BLE Core and the digital PHY of the Radio.
The above mentioned are the different power domains in the chip that can be enabled/disabled individually in each of the power saving modes.
For further details, refer to the DA14531 datasheet or DA14535 datasheet section 4.2.2.2, for more extensive content on the same.
Block explanation
AMBA AHB (Advanced Micro controller Bus Architecture, Advanced High-performance Bus): DA1453x is based on this, and is used to connect components that need high bandwidth.
DMA Engine (Direct memory Access) : connected to AHB bus as master and has the highest priority to copy code from OTP into SysRAM.
CRG (Clock and Reset Generator) :This block is responsible for generating the clock signals and system reset.
WIC (Wake-up Interrupt Controller) : to allow the processor to be powered down during sleep, while interrupt sources are still allowed to wake up the system
A summary of the power modes, the digital power domains, as well as the clocks and wake-up capabilities are explained in Figure below.
Power Mode |
Digital Power Domains |
VDD Level,DCDC Converter,LDOs |
Clock Availability |
SysRAM Retention |
Wake Up Sources |
|---|---|---|---|---|---|
Active or Sleep (WFI) |
PD_AON = ON PD_SLP = ON PD_SYS = ON PD_TIM = OPTIONAL PD_RAD = OPT |
VDD=0.9 V DCDC = ON (Buck or Boost) LDO_LOW = OFF LDO_CORE = ON, Active (0.9 V) VDD_Clamp = OFF LDO_RADIO = Programmable |
All |
SysRAM1 = ON (Application) SysRAM2 = optionally retained SysRAM3 = ON (Stack Data) |
|
Extended Sleep (with or without OTP) |
PD_AON = ON PD_SLP = ON PD_SYS = OFF PD_TIM = OPTIONAL PD_RAD = OFF |
VDD=0.75V DCDC = OFF LDO_LOW = ON, in Buck mode LDO_CORE = ON, Active (0.75V) VDD_Clamp = OFF LDO_RADIO = OFF |
RCX or XTAL32K |
SysRAMx = optionally retained typically only SysRAM1 is retained) |
|
Deep Sleep |
PD_AON = ON PD_SLP = ON PD_SYS = ON PD_TIM = OPTIONAL PD_RAD = OPT |
VDD=0.75V DCDC = OFF LDO_LOW = ON,in Buck mode LDO_CORE = ON,in retain mode (0.75 V) VDD_Clamp = OFF LDO_RADIO = OFF |
RCX or XTAL32K |
SysRAMx = optionally retained (Typically OFF) |
|
Hibernation |
PD_AON = ON PD_SLP = ON PD_SYS = ON PD_TIM = OPTIONAL PD_RAD = OPT |
VDD=0.75V DCDC = OFF LDO_LOW = OFF LDO_CORE = OFF VDD_Clamp =~0.75v LDO_RADIO = OFF |
No Clocks |
SysRAMx = optionally retained |
Wake up from P0_1, P0_2,P0_3, P0_4, P0_5 |
Warning
PD_TIM: is marked as “OPTIONAL” in each power mode, indicating that its activation is not mandatory.
PD_RAD: is marked as “OPT” (Optional) in Active or Sleep (WFI) mode but “OFF” in Extended Sleep and Deep Sleep modes.
LDO_RADIO: is marked as “Programmable” in Active or Sleep (WFI) mode, “OFF” in Extended Sleep, and “OFF” in Deep Sleep.
SysRAMx: refers to different levels of System RAM, and the table indicates whether they are retained or optionally retained in each power mode.
4. Sleep modes hardware overview (DA1458x)
Similar to the DA14531, the sleep modes are configured by #defines in the SDK. The DA14585 comprises several different power domains that are controlled by power switching elements, thus eliminating leakage currents by totally powering them down. The partitioning of the DA14585’s resources with respect to the various power domains is presented in the table below,
Domain Name |
Description |
|---|---|
PD_AON |
Always powered domain. This power line connects to all the resources that must be powered constantly: the ARM/WIC, the LLP/Timer, the PMU/CRG, the Capture Timer, the Quadrature Decoder, the pad ring and various registers required for the Wake Up sequence. |
PD_SYS |
System Power Domain. This power line connects to all the resources that should be powered only when the ARM M0 is running: the AHB bus, the OTP cell and controllers, the ROM, the SysRAM the Watchdog, the SW Timer and the GPIO port multiplexing. |
PD_PER |
Peripherals Power Domain. This power line connects to the peripherals that can be switched off after completing their operation: the UARTs, the SPI, the I2C the Keyboard controller, the ADC and the Audio Unit. |
PD_DBG |
Debug Power Domain. It Powers the debug part of the ARM Cortex-M0 processor. |
PD_RAD |
Radio Power Domain. It comprises of the BLE Core and the digital PHY of the Radio. The power management of the Radio (RF) subsystem is controlled via several dedicated LDOs. |
PD_SR1 |
SysRAM1. This is a separate power line that only controls the first 32 kB SysRAM cell. If this memory cell is not needed, it should always be OFF. |
PD_SR2 |
SysRAM2. This is a separate power line that only controls the first 16 kB SysRAM cell. If this memory cell is not needed, it should always be OFF. |
PD_SR3 |
SysRAM3. This is a separate power line that only controls the second 16 kB SysRAM cell. If this memory cell is not needed, it should always be OFF. |
PD_SR4 |
SysRAM4. This is a separate power line that only controls the second 32 kB SysRAM cell. If this memory cell is not needed, it should always be OFF. |
For further details, refer to the DA14585 datasheet section 4.5, for more extensive content on the same.
- The DA1458x has 2 sleep modes available:
Extended sleep mode: All power domains are off except for the PD_AON and the programmed PD_SRx. OTP mirroring is required upon waking up the system when the application code and data are not retained. If the system code is mirrored from an external flash the corresponding SysRam cells are retained and no OTP mirroring is performed upon wake up. The device will wake up from an external interrupt or BLE timer.
Deep Sleep mode: All power domains are off including all the SysRAM cells. A BLE connection cannot be maintained. The system will wake up only from an external interrupt (HW reset on wakeup) or from a Power-On Reset source. In this mode the system consumes the minimum amount of power.
4.1. Hardware Setup
- This example runs on the BLE Smart SoC (System on Chip) devices:
DA14531/DA14585-586 daughter board + DA14531DEVKT-P.
or
DA14535 daughter board + DA1453xDEVKT-P
The user manuals for the development kits can be found here.
The figure below shows the hardware setup (DA14531) for the SPI Flash.
Figure 6 Hardware setup (DA14531) with SPI Flash and jtag jumpers placed
The figure below shows the hardware setup (DA14535) for the SPI Flash.
Figure 7 Hardware setup (DA14535) with SPI Flash and jtag jumpers placed
Note
Similar setup with the DA14585 is shown below. Only the daughterboard is replaced and rest is similar to that of DA14531 for all the setup.
The figure below shows the hardware setup (DA14585) for the SPI Flash.
Figure 8 Hardware setup (DA14585) with SPI Flash and jtag jumpers placed
- If you want to run the firmware from SysRAM or OTP, the SPI related jumpers can be taken off:
Figure 9 Hardware setup with jtag jumpers placed (DA14531 DEVKT-P , DA14531)
Figure 10 Hardware setup with jtag jumpers placed (DA1453x DEVKT-P , DA14535)
- To run the device in Boost mode, re-arrange the jumper J4 to J4[1-2] and remove the jumpers from J5 on the motherboard, as shown in the picture below.
Figure 11 Hardware setup with jtag jumpers and boost mode (DA14531 DEVKT-P , DA14531)
Note
The above setup is the same for DA1458x devices. Only replace the DA14531 with a DA1458x daughterboard.
Figure 12 Hardware setup with jtag jumpers and boost mode (DA1453x DEVKT-P , DA14535)