2. Sleep modes overview

To give an overview of the sleep modes available, the following section will give more idea on each mode and its application.

The block diagram of the DA14531 is as shown below and the highlighted red box is where the retention memory blocks are placed and this includes SysRAM1 (16kB), SysRAM2 (12kB) and SysRAM3 (20kB). So a total of 48kB system RAM is available.

_images/blockdiag.png

Figure 1 DA14531 Block Diagram

The DA14585 block diagram is as shown below with the highlighted red box indicating the retention memory blocks. In total there is 96kB system RAM available, divided in 4 RAM blocks - SysRAM1 (32kB), SysRAM2 (16kB), SysRAM3 (16kB) and SysRAM4 (32kB).

_images/blockdiag_585.png

Figure 2 DA14585 Block Diagram

  1. Extended Sleep mode

    • In Extended sleep mode, the system domain except the SysRAM, the radio domain and the peripheral domain are powered down and the XTAL16M clock is stopped. The SysRAM is still powered to retain data but is not accessible.

    • The AON power domain is ON to keep data in the retention RAMs and to supply power to the blocks that can wake the system up, i.e. wakeup timer, quadrature decoder and the BLE timer.

  2. Deep sleep mode

    • In Deep sleep mode, to reduce the power consumption even further, the SysRAM is also powered off. The status of the other power domains is the same as in Extended sleep mode.

    • The device can wake-up from deep sleep either using clocked-wake up controller, from GPIOs, RTC alarm (ONLY on DA14531) or Timer1 (ONLY on DA14531).

  3. Hibernation sleep mode (ONLY on DA14531)

    • In Hibernation mode as compared to previous two sleep modes, the PD_SLP (Sleep power domain) domain is switched off. This means the CRG (Clock and Reset Generator) is powered off and this is why this mode is called Clock-less mode.

    • The device can wake-up from only GPIOs that is configured to wake-up. The available GPIOs to wake the device up from hibernation is P0_1, P0_2 … P0_5.

3. Sleep modes hardware overview (DA14531)

Sleep modes are configured by #defines in the SDK. However, this section explains the hardware power domains and how these are configured in each of the sleep modes. The sleep mode in general has no power gating programmed. The ARM CPU is idle and waiting for an interrupt, PD_SYS is on whereas PD_TIM and PD_RAD depend on the programmed enabled value.

To know which power domain powers what part of the blocks, refer to the below figure on mapping of digital power domains and blocks,

_images/powerblock.png

Figure 3 DA14531 Mapping of Digital Power Domains and Blocks

For example, the PD_SYS powers up the SysRAM blocks as seen in the figure above.

  • AMBA AHB (Advanced Micro controller Bus Architecture, Advanced High-performance Bus)- DA14531 is based on this, and is used to connect components that need high bandwidth.

  • DMA Engine (Direct memory Access) - connected to AHB bus as master and has the highest priority to copy code from OTP into SysRAM.

  • CRG - Clock and Reset Generator - This block is responsible for generating the clock signals and system reset.

  • WIC - Wake-up Interrupt Controller - to allow the processor to be powered down during sleep, while interrupt sources are still allowed to wake up the system

The description of the power domain is mentioned in the table below,

Table 1 DA14531 Power Domains Description

Domain Name

Description

PD_AON

Always powered domain. It contains a Clock-less Wake Up controller and the pad-ring.

PD_SLP

Sleep power domain. It comprises of the ARM/WIC (Wake-up Interrupt controller, the BLE Timer, the PMU/CRG, the Clocked Wakeup Controller, the Quadrature Decoder, and various registers required for the Wake-Up sequence.

PD_SYS

System Power Domain. It comprises of the AHB bus, the OTP cell and controllers, the ROM, the System RAM, the Watchdog, the SW Timer, and the GPIO port multiplexing.

PD_TIM

Timer Power Domain. It comprises of the RTC and the Timer1. These two blocks can be active during the sleep modes.

PD_RAD

Radio Power Domain. It comprises of the BLE Core and the digital PHY of the Radio.

The above mentioned are the different power domains in the chip that can be enabled/disabled individually in each of the power saving modes.

For further details, refer to the DA14531 datasheet section 4.2.2.2, for more extensive content on the same.

The DA14531 has 3 sleep modes available:

  1. Extended sleep mode: PD_AON, PD_SLP, and conditionally PD_TIM are active. RAM is expected to be retained for:

    • Keeping a BLE connection alive (stack variables or BLE data)

    • Potentially keep the application code and it can be omitted if the OTP (One-Time Programmable) is instructed to automatically get mirrored into RAM upon every wake up

  2. Deep Sleep mode: Shipping clocked mode with all domains is disabled. RAM may or may not be retained. RTC ticking is programmable.

  3. Hibernation mode: Shipping clock-less mode with all domains is disabled. RAM may or may not be retained. No clock is running.

A summary of the power modes, the digital power domains, as well as the clocks and wake-up capabilities are explained in Figure 1 below.

_images/powerdomain_summary.png

Figure 4 Power Modes, Digital Power Domains, Clocks, and Wake-up triggers

4. Sleep modes hardware overview (DA14585/586)

Similar to the DA14531, the sleep modes are configured by #defines in the SDK. The DA14585 comprises several different power domains that are controlled by power switching elements, thus eliminating leakage currents by totally powering them down. The partitioning of the DA14585’s resources with respect to the various power domains is presented in the table below,

Table 2 DA14585 Power Domains Description

Domain Name

Description

PD_AON

Always powered domain. This power line connects to all the resources that must be powered constantly: the ARM/WIC, the LLP/Timer, the PMU/CRG, the Capture Timer, the Quadrature Decoder, the pad ring and various registers required for the Wake Up sequence.

PD_SYS

System Power Domain. This power line connects to all the resources that should be powered only when the ARM M0 is running: the AHB bus, the OTP cell and controllers, the ROM, the SysRAM the Watchdog, the SW Timer and the GPIO port multiplexing.

PD_PER

Peripherals Power Domain. This power line connects to the peripherals that can be switched off after completing their operation: the UARTs, the SPI, the I2C the Keyboard controller, the ADC and the Audio Unit.

PD_DBG

Debug Power Domain. It Powers the debug part of the ARM Cortex-M0 processor.

PD_RAD

Radio Power Domain. It comprises of the BLE Core and the digital PHY of the Radio. The power management of the Radio (RF) subsystem is controlled via several dedicated LDOs.

PD_SR1

SysRAM1. This is a separate power line that only controls the first 32 kB SysRAM cell. If this memory cell is not needed, it should always be OFF.

PD_SR2

SysRAM2. This is a separate power line that only controls the first 16 kB SysRAM cell. If this memory cell is not needed, it should always be OFF.

PD_SR3

SysRAM3. This is a separate power line that only controls the second 16 kB SysRAM cell. If this memory cell is not needed, it should always be OFF.

PD_SR4

SysRAM4. This is a separate power line that only controls the second 32 kB SysRAM cell. If this memory cell is not needed, it should always be OFF.

For further details, refer to the DA14585 datasheet section 4.5, for more extensive content on the same.

The DA14585/586 has 2 sleep modes available:

1) Extended sleep mode: All power domains are off except for the PD_AON and the programmed PD_SRx. OTP mirroring is required upon waking up the system when the application code and data are not retained. If the system code is mirrored from an external flash the corresponding SysRam cells are retained and no OTP mirroring is performed upon wake up. The device will wake up from an external interrupt or BLE timer.

2) Deep Sleep mode: All power domains are off including all the SysRAM cells. A BLE connection cannot be maintained. The system will wake up only from an external interrupt (HW reset on wakeup) or from a Power-On Reset source. In this mode the system consumes the minimum amount of power.

4.1. Hardware Setup

This example runs on the BLE Smart SoC (System on Chip) devices: - DA14531/DA14585-586 daughter board + DA145xxDEVKT-P PRO-Motherboard.

The user manuals for the development kits can be found here.

The figure below shows the hardware setup (DA14531) for the SPI Flash.

_images/spi.png

Figure 5 Hardware setup (DA14531) with SPI Flash and jtag jumpers placed

Note

Similar setup with the DA14585 is shown below. Only the daughterboard is replaced and rest is similar to that of DA14531 for all the setup.

The figure below shows the hardware setup (DA14585) for the SPI Flash.

_images/spi_585.png

Figure 6 Hardware setup (DA14585) with SPI Flash and jtag jumpers placed

If you want to run the firmware from SysRAM or OTP, the SPI related jumpers can be taken off.

_images/jtag.png

Figure 7 Hardware setup with jtag jumpers placed

To run the device in Boost mode, re-arrange the jumper J4 to J4[1-2] and remove the jumpers from J5 on the motherboard, as shown in the picture below.

_images/boost.png

Figure 8 Hardware setup with jtag jumpers and boost mode

Note

The above setup is the same for DA14585/586 devices. Only replace the DA14531 with a DA14585/586 daughterboard.